Documenting RTL Designs with Graphziv/Graphs with a lot of feedback/Controlling rank

Hello,
I just found out about Graphviz.  My interest is in documenting the architecture of RTL (verilog) based designs.  I have found it quite useful for (finite) state machine documentation.  Then I tried to document an arithmetic logic circuit with a lot of feedback.  I found that GraphViz's placement of many node led to a confusing diagram.  For example, I am using nodes to represent digital logic structures such as registers, ram memories, muxes, adders, multipliers, other RTL modules, etc.  If I have a mux output going to the input of a register, I would almost always like to force the mux to be of a higher rank than the register (GraphViz often violated this in node placement).  But the rank options of min/max/same/source/sink do not appear to be adequate.  If there were greater than/less than rank operaters that could be applied to pairs (or groups) of nodes, I think that could solve my problem.
Does anyone have any suggestions?  Thanks.
 
Jitter.txt is a GraphViz dot file. 
For example, I'd like to force
jitter_acc_mux_nxt
to be to the left of:
jitter_acc.
 
- Scott

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Jitter.txt6.27 KB

jitter.txt

Jitter.txt is a GraphViz dot file. 
For example, I'd like to force
jitter_acc_mux_nxt
to be to the left of:
jitter_acc.

jitter.txt

Jitter.txt is a GraphViz dot file. 
For example, I'd like to force
jitter_acc_mux_nxt
to be to the left of:
jitter_acc.

Documenting RTL Designs with

An edge in the dot layout is precisely a greater than/less than operator. That is, if you have an edge a->b, then in general the node a will be placed on a rank above the node b. There are two main ways when this will fail: if your graph has cycles, in which case, dot will reverse some edges, or if your graph uses clusters. In the latter case, dot traditionally draws clusters as compactly as possible, which may induce a global violation of an edge constraint. The new cgraph-based version of dot allows you to avoid this problem.
If you want more concrete suggestions, it may be helpful to post a sample graph and point out what you don't want in the drawing.

example file

Attached jitter.txt is a GraphViz dot file.
For example, I'd like to force
jitter_acc_nxt_mux
to be to the left of
jitter_acc.

example file

First, if you want jitter_acc_nxt_mux to be to the left of jitter_acc, get rid of constraint=false in the edge. It is precisely having constraint=true (the default) that will keep jitter_acc_nxt_mux to the left of jitter_acc.
Next, as I noted before, if your graph has cycles, some edges are reversed to make the graph acyclic. You have to make sure that the edge jitter_acc_nxt_mux -> jitter_acc is not reversed. To do this, if must be visited before the edge jitter_acc -> jitter_acc_nxt_mu. Edges are visited in order of their tail nodes, and nodes are ordered by when they appear in the graph. So to get what you want, just make  jitter_acc_nxt_mu the first node listed in the graph.

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