Number: 1001
Title: Layout doesn't take head and tail labels into account
Submitter: Bert Rodiers
Date: Tue Aug 22 12:42:21 2006
Subsys: Dot
Version: 2.8
System: x86-Windows-XP
Severity: critical
When you generate a layout the head and tail labels often overlap and the connection points all come to the same place of the node, while in most generated diagrams there seems to be space enough to better spread the connection points and labels. For us this is critical since it makes the diagrams often very difficult to interpret.
Input file:
Output file: b1001.jpg
[north] Bert, this is not so much a bug as it is a missing feature.

If you know where to find good CPL-compatible code for maintaining planar subdivisions with polys and splines that would be helpful. Maybe some kind of (throat clearing here) simulated annealing code or constraint satisfaction code could get the job done but right now we don't even have a data structure that would "know" there is plenty of space in which to move head and tail labels.
Owner: *
Status: Request